1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly, to an improvement of a semiconductor memory device in which each memory cell includes at least one MOS transistor and one capacitor.
2. Description of the Prior Art
Recently a semiconductor memory device having high memory capacity and density such as 16 k bits and 64 k bits has been developed. As the structure of the semiconductor memory device, a dynamic memory cell type device wherein each memory cell has one MOS transistor and one capacitor has been used in various fields. In the dynamic memory cell type device, the data of "1" or "0" are memorized in the form of charges stored in the capacitor. Thus, the capacitor should have a relatively large capacitance, resulting in a correspondingly large size. The miniaturization of the area of the memory cell is prevented because of the area of the capacitor whereby a semiconductor memory device having a memory capacity greater than 64 k bits could not be practically attained.
FIG. 1 is a cross-sectional view of the structure of a conventional memory cell wherein a thick partition oxide layer (2) for partitioning elements is formed on a surface of a P-silicon substrate (1) and a p.sup.+ -layer (3) having high impurity concentration for preventing turnover of the P-silicon substrate (1) to n-type is also formed on the surface of the P-silicon substrate (1). The MOS transistor is formed by a thin gate oxide layer (4) a first polysilicon layer (5) for a gate electrode and wiring, and a n+ diffused layer (6) having high impurity concentration for bit lines of the memory.
The capacitor part is forme by an insulating oxide layer (7) sandwiched between a P-silicon substrate (1) and a second polysilicon layer (8) placed on both sides thereof and serving as counter electrodes.
In the memory cell, all parts of the structure are covered by a thick silicon oxide layer (9) formed by a CVD process. An opening is formed on the first polysilicon layer (5) for the gate electrode and an aluminum wiring layer (10) connected to the first polysilicon layer (5) is formed.
As shown in FIG. 1, the gate of the MOS transistor and the capacitor are formed on one plane in the conventional device. Thus, in order to reduce the size of the memory cell, it is necessary to reduce the area of the capacitor. However, if the area of the capacitor is reduced, the capacitance thereof is also reduced, such that data memorized in the form of the electric charges stored in the capacitor are subject to change by naturally occurring .alpha.-rays whereby "soft error" is easily caused.